Computer Memory Module is a Pneumatic Parts product. Key specs — Origin: China (Mainland).
Product Description
Model No.:Market General Model Product
Origin:China Brand
Name:
Price Terms:FOB, EXW
Payment Terms:T/T, L/C
Certification: Description:
Specifications: DDR1) 400MHz, 333MHz 2) 184-pin socket type dual in line memory module (DIMM) 3) 2.6V power supply 4) Data rate: 400Mbps (max.) 5) 2.5 V (SSTL-2 compatible) I/O 6) Double data rate structure: two data transfers per clock cycle 7) Bi-directional, data strobe (DQS) is transmitted / received with data, to be used in capturing data at the receiver 8) Data inputs and outputs are synchronized with DQS 9) DQS is edge aligned with data for read; center aligned with data for write 10) Differential clock inputs (CK and /CK) 11) DLL aligns DQ and DQS transitions with CK transitions 12) Commands entered on each positive CK edge; data referenced to both edges of DQS 13) Auto pre-charge option for each burst access 14) Programmable burst length: 2, 4, 8
Specification: DDR21) 533MHZ, 667MHZ 2) 240-pin socket type dual in line memory module (DIMM), lead-free 3) 1.8V power supply 4) Data rate: 533Mbps, 667Mbps 5) 1.8V (SSTL-18 compatible) I/O 6) Double-data-rate architecture: two data transfers per clock cycle 7) Bi-directional, differential data strobe (DQS and/DQS) is transmitted/received with data, to be used in capturing data at the receiver 8) DQS is edge aligned with data for reads: center aligned with data for writes 9) Differential clock inputs (CK and CK) 10) DLL aligns DQ and DQS transitions with CK transitions 11) Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 12) Four internal banks for concurrent operation (component) 13) Data mask (DM) for write data 14) Burst lengths: 4, 8 15) CAS latency (CL): 3, 4, 5 16) Auto pre-charge operation for each burst access 17) Auto refresh and self refresh modes 18) 7.8us average periodic refresh interval 19) Posted CAS by programmable additive latency for better command and data bus efficiency20) Off-chip-driver impedance adjustment and on-die-termination for better signal quality 21) DQS can be disabled for single-ended data strobe operation
